Thomas Poonnen was born in the late seventies in Kerala, India. He belongs to the Palampadom family, an ancient Christian family from India. He is the only child of Mrs. & Mr. Thomas Palampadom. He is married to Breeta Erali Elbi, and they have a daughter, Nikita. He resides with his family at the CasaBreeta [+] in Greater Los Angeles, California, USA.
He has two decades of progressive experience in integrated circuit (IC) design, with expertise in digital image sensor design (ultraviolet / visible / infrared). He has been the technical lead for several CMOS image sensor (CIS) and readout integrated circuit (ROIC) products from conception to productization. He has served as the Principal Investigator / Key Person on multiple research grants (DoD, NASA). He is presently the Director of Engineering at Senseeker Engineering that specializes in the design of state-of-the-art digital ROICs for advanced infrared imaging applications.
He has a Doctor of Philosophy (Ph.D.) degree in Electrical Engineering from the State University of New York at Buffalo, USA, a Master of Science (M.S.) degree in Electrical Engineering from the State University of New York at Buffalo, USA, and a Bachelor of Technology (B.Tech.) degree in Electrical and Electronics Engineering from the University of Kerala, India.
He has several patents and technical publications to his credit. He is a Senior Member of the IEEE, and a Member of the SPIE, the ASME and the PMI.
Experience
Director of Engineering, 2014 - present
Senseeker Engineering, USA
★ Advanced digital readout integrated circuits (DROICs) and digital pixel readout integrated circuits (DPROICs) for various infrared imaging applications
Principal/Senior Engineer, 2004 - 2014
Panavision, USA (Panavision Imaging and spin-off)
★ Ultra high-definition CMOS image sensors for cinematography and scientific applications
★ High-definition CMOS image sensors for automotive, industrial & security applications
★ Specialized CMOS line-scan sensors for touch-screen applications
(+ other technical experience)
Education
Doctor of Philosophy (Ph.D.), Electrical Engineering, 2007
State University of New York at Buffalo, USA
★ Dissertation: Efficient VLSI Divide and Conquer Array Architectures for Multiplication
Master of Science (M.S.), Electrical Engineering, 2003
State University of New York at Buffalo, USA
★ Thesis: An Area-Efficient VLSI Implementation for Programmable FIR Filters based on a Parameterized Divide and Conquer Approach
Bachelor of Technology (B.Tech.), Electrical and Electronics Engineering, 1999
University of Kerala, India
(+ professional certifications)
Dissertation / Thesis
★ T. Poonnen, “Efficient VLSI Divide and Conquer Array Architectures for Multiplication,” Doctor of Philosophy Dissertation, Department of Electrical Engineering, State University of New York at Buffalo, USA, September 1, 2007.
★ T. Poonnen, "An Area-Efficient VLSI Implementation for Programmable FIR Filters based on a Parameterized Divide and Conquer Approach," Master of Science Thesis, Department of Electrical Engineering, State University of New York at Buffalo, USA, September 1, 2003.
Journals / Conferences
★ T. Poonnen, N. Dhawan, W. Korth, and K. Veeder, "Digital Pixel Readout Integrated Circuit for High Dynamic Range Infrared Imaging," Proceedings of SPIE Defense + Commercial Sensing Conference, June 13, 2023. [+]
★ T. Poonnen, W. Korth, C. Peterson, and K. Veeder, "Proximal Interpolation, Tone Mapping and Pseudo-Coloring for Intra-Frame High Dynamic Range Infrared Imaging," Proceedings of SPIE Defense + Commercial Sensing Conference, May 27, 2022. [+]
★ T. Poonnen, S. McCotter, K. Esparza, and K. Veeder, "Digital Readout Integrated Circuit for High Dynamic Range Infrared Imaging," Proceedings of SPIE Defense + Commercial Sensing Conference, April 12, 2021. [+]
★ T. Poonnen, and A. T. Fam, "An Area-Efficient VLSI Implementation for Programmable FIR Filters based on a Parameterized Divide and Conquer Approach," Elsevier Journal of Systems Architecture 54 (12), December 1, 2008. [+]
★ T. Poonnen, L. Liu, K. V. Karia, M. E. Joyner and J. J. Zarnowski, "A CMOS Video Sensor for High Dynamic Range (HDR) Imaging," Proceedings of IEEE Asilomar Conference on Signals, Systems and Computers (ACSSC), October 29, 2008. [+]
★ T. Poonnen, and A. T. Fam, "A Novel VLSI Divide and Conquer Array Architecture for Vector-Scalar Multiplication," Proceedings of IEEE International Conference on Integrated Circuit Design and Technology (ICICDT), June 1, 2007. [+]
★ T. Poonnen, and A. T. Fam, "A Novel VLSI Divide and Conquer Implementation of the Iterative Array Multiplier," Proceedings of IEEE International Conference on Information Technology – New Generations (ITNG), April 4, 2007. [+]
★ T. Poonnen, and A. T. Fam, "An Area-Efficient VLSI Implementation for Programmable FIR Filters based on a Parameterized Divide and Conquer Approach," Proceedings of IEEE International Conference on Microelectronics (ICM), December 11, 2003. [+]
(+ other technical publications)
Patents
★ T. Poonnen, J. J. Zarnowski, L. Liu, M. E. Joyner, and K. V. Karia, IMAGE SENSOR ADC AND CDS PER COLUMN WITH OVERSAMPLING, United States Patent No. 8,169,517, filed October 16, 2007 and issued May 1, 2012. [+]
★ L. Liu, J. J. Zarnowski, K. V. Karia, T. Poonnen, and M. E. Joyner, SUB-PIXEL ARRAY OPTICAL SENSOR, United States Patent No. 8,035,711, filed May 22, 2008 and issued October 11, 2011. [+]
★ J. J. Zarnowski, K. V. Karia, T. Poonnen, and M. E. Joyner, IMAGE SENSOR ADC AND CDS PER COLUMN, United States Patent No. 7,903,159, filed April 10, 2009 and issued March 8, 2011. [+]
★ J. J. Zarnowski, K. V. Karia, M. E. Joyner, T. Poonnen, and L. Liu, SCANNING IMAGER EMPLOYING MULTIPLE CHIPS WITH STAGGERED PIXELS, United States Patent No. 7,554,067, filed October 30, 2006 and issued June 30, 2009. [+]
★ J. J. Zarnowski, K. V. Karia, and T. Poonnen, IMAGE SENSOR ADC AND CDS PER COLUMN, United States Patent No. 7,518,646, filed September 20, 2005 and issued April 14, 2009. [+]
★ J. J. Zarnowski, K. V. Karia, M. E. Joyner, T. Poonnen, SCANNING IMAGER EMPLOYING MULTIPLE CHIPS WITH STAGGERED PIXELS, United States Patent No. 7,129,461, filed May 16, 2006 and issued October 31, 2006. [+]
★ J. J. Zarnowski, K. V. Karia, M. E. Joyner, T. Poonnen, SCANNING IMAGER EMPLOYING MULTIPLE CHIPS WITH STAGGERED PIXELS, United States Patent No. 7,122,778, filed February 17, 2006 and issued October 17, 2006. [+]
★ J. J. Zarnowski, K. V. Karia, M. E. Joyner, T. Poonnen, SCANNING IMAGER EMPLOYING MULTIPLE CHIPS WITH STAGGERED PIXELS, United States Patent No. 7,045,758, filed April 21, 2005 and issued May 16, 2006. [+]
(+ international patents)
© Thomas Poonnen. All Rights Reserved.